[time-nuts] Interfacing of 74ALVC divider chain to ADF4350 output (yet another low jitter sine-to-logic thread ; ) )

[Attila Kinali]

On Sun, 30 Jul 2017 23:52:50 +0300
Yuri Ostry <yuri at ostry.ru> wrote:

> But interfacing of 74ALVC flip-flop input to a ADF output in a 160-260 MHz
> range is not so easy question for me, especially taking low jitter
> requirements into account. Maybe someone can share tested working solution that
> will not add too much noise and will be more or less stable with
> temperature variations?

CMOS signals get a bit iffy when going over 100MHz. You will probably
have to build your own board for the divider. I don't think it would
be reliable without it. As for interfacing the ADF4350 output, you will
need to use the differential output to cross the board-to-board gap.
On the divider board use a differential pair to convert the signal
to proper CMOS levels. You can use the one in the TADD2 or TICC
as an example how to do it. Make sure the f_t of the transistors
is high enough and that you give them enough current to work with.
Keep all wires on the divider board short and remove all planes
underneath the circuit, safe for the (closed) ground plane on the
bottom layer, in order to minimize stray capacitance.

Alternatively, use something like an SY89874 as first divider
stage  to get down to a more managable frequency range, then
continue with your ALVC dividers.

			Attila Kinali

-- 
You know, the very powerful and the very stupid have one thing in common.
They don't alters their views to fit the facts, they alter the facts to
fit the views, which can be uncomfortable if you happen to be one of the
facts that needs altering.  -- The Doctor