[time-nuts] Using CPLD/FPGA or similar for frequency divider

Hal Murray hmurray at megapathdsl.net
Tue Jun 2 22:35:29 UTC 2015

david.partridge at perdrix.co.uk said:
> Is this a sensible thing to consider doing?  Or would I be better sticking
> to AC/HC/AHC/LVC logic?

A CPLD is a fine way to divide by a large number.  Even the smaller FPGAs are 
probably overkill but they should work fine.

If you are interested in jitter, the main problem is due to shared 
power/ground lines.  With things like a CPLD, the usual way to get in trouble 
is to put several unrelated chunks of logic into the same chip.  If you only 
have a single divider in a chip, I'd expect the output to be clean.

You can get the same problem with AC/LVC scale logic with multiple sections 
if you use the sections for unrelated logic.  That's one of the reasons the 
modern single gate packages work so well.  You can't screwup and put two (or 
more) unrelated chunks of logic in the same chip.

These are my opinions.  I hate spam.

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