[time-nuts] Using CPLD/FPGA or similar for frequency divider

Bruce Griffiths bruce.griffiths at xtra.co.nz
Wed Jun 3 00:31:21 UTC 2015

On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote:
> Is this a sensible thing to consider doing?  Or would I be better sticking
> to AC/HC/AHC/LVC logic?
> Regards,
> David Partridge
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It makes it easier to implement low noise lambda dividers which overcome 
most of the PN degradation of digital dividers.
Also the FPGA can easily be reconfigured to produce outputs different from 
those originally implemented.


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