[time-nuts] Using CPLD/FPGA or similar for frequency divider
David C. Partridge
david.partridge at perdrix.co.uk
Sun Jun 7 10:23:40 UTC 2015
My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... .
Bruce pointed me to Rubiola's paper <http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf>, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here.
My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages. I don't think it makes sense to use a CPLD if you need to use a separate package for each stage.
I'm also a bit concerned by Bob Camp's comment:
>they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS
which suggests that it will be (at least 10dB) worse than my existing design :(
I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA.
I'm also a bothered by the findings in <http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf> which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as "Mature" so may be at risk of obsolescence
Thanks to all for the discussion to date.
(*) similar to my previous effort made with 74AC logic.
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