[time-nuts] Using CPLD/FPGA or similar for frequency divider
kb8tq at n1k.org
Sun Jun 7 21:13:19 UTC 2015
As always, the real answer is “that depends”.
If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to the question. It will give you some cool bells and whistles (like sync and advance / retard) without adding anything to the budget. If you wish to re-sync the output with a single gate D-FF running on the “wrong edge” of the 10 MHz, that’s easily done and it adds virtually nothing to the board space or cost.
If you are building a low noise PLL and going from 160 MHz down to a 40 MHz analog phase detector (with a floor of -170 dbc/ Hz), the CLPD or FPGA isn’t a good choice. You can do the complete divide with a single package part and get lower noise.
The board with the 160 MHz PLL on it is going to be a single purpose layout and it will live it’s life doing one thing. The board with the 1 pps
divider might get re-purposed to do a variety of things. A “universal” FPGA board with some basic timing stuff (connectors / re-sync flip flops / input gates) on it might be a very useful thing to have around …..
> On Jun 7, 2015, at 6:23 AM, David C. Partridge <david.partridge at perdrix.co.uk> wrote:
> My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... .
> Bruce pointed me to Rubiola's paper <http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf>, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here.
> My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages.
Internal cross talk on FPGA’s and CPLD’s is pretty much a non-issue. That assumes that the board is properly laid out and the supplies are
well bypassed. Input and output cross talk can be reduced (but not always eliminated) by running differential inputs and putting “threat” signals on different i/o banks from each other.
The “properly laid out” constraint with a FPGA / CPLD forces you to a > 2 layer board pretty fast. Depending on the density and a few other things you may be past 6 layers. Yes that costs money.
> I don't think it makes sense to use a CPLD if you need to use a separate package for each stage.
> I'm also a bit concerned by Bob Camp's comment:
>> they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS
> which suggests that it will be (at least 10dB) worse than my existing design :(
> I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA.
> I'm also a bothered by the findings in <http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf> which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as "Mature" so may be at risk of obsolescence
> Thanks to all for the discussion to date.
> (*) similar to my previous effort made with 74AC logic.
> Thanks again
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