[time-nuts] Generating a solid PPS from 10Mhz source

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Jan 15 09:14:14 UTC 2016

For lowest jitter the gate power supply noise needs to be very low.Biasing the input at 50% supply helps somewhat but the gate threshold is never exactly 50% and the low pass filtering effect of the coupling capacitor increases the contribution of power supply noise to jitter.
A power supply noise below 10nV/rtHz is probably required to achieve the lowest jitter. Few regulators achieve this particularly at low frequencies.


    On Friday, 15 January 2016 8:10 PM, Charles Steinmetz <csteinmetz at yandex.com> wrote:

 Nick wrote:

>The output from my GPSDO is a square wave, so I didn't condition the 
>input. In the past what I've used for that is a DC blocking cap, 
>followed by a Thevenin termination (100 ohms to ground and Vcc) 
>feeding a 74LVC1G17 Schmitt trigger buffer. I don't know if that's 
>up to Time Nuts standard or not. The one downside I've seen with it 
>is that it kind of requires a larger input amplitude than is 
>sometimes convenient.

You will get less jitter (as well as more sensitivity) if you use a 
buffer without a Schmitt input (it should also be "native" CMOS -- 
with an input threshold of 1/2 Vcc -- not CMOS with TTL input 
thresholds).  For best performance, the input signal should be scaled 
to drive the buffer input quite close to both logic power supply 
rails.  You can use Shottky diodes (1N5711, 1N6263) to clamp the 
buffer input to 0 and Vcc if necessary (I would include such diodes 
as a best practice, even if I did not expect input excursions beyond 
the rails).

Best regards,


time-nuts mailing list -- time-nuts at febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.


More information about the Time-nuts_lists.febo.com mailing list