[time-nuts] Generating a solid PPS from 10Mhz source

Gerhard Hoffmann dk4xp at arcor.de
Sun Jan 17 16:32:58 UTC 2016

Am 15.01.2016 um 10:14 schrieb Bruce Griffiths:
> For lowest jitter the gate power supply noise needs to be very low.Biasing the input at 50% supply helps somewhat but the gate threshold is never exactly 50% and the low pass filtering effect of the coupling capacitor increases the contribution of power supply noise to jitter.
> A power supply noise below 10nV/rtHz is probably required to achieve the lowest jitter. Few regulators achieve this particularly at low frequencies.
I have recently measured the noise of some regulators, LEDs and Zeners 
with partly unexpected results.
I'll do a write-up and put it on my web site, but here are 3 pictures 
that already tell a lot:



Note the low 1/f corner of the BZX84 C2V7 and 3V3.
And 0 dB is the noise of a 60 Ohm resistor, or the INPUT referred noise 
of an AD797 or LT1028.

LEDs abused as References:

The Avago HLMP-6000 is the clear winner in terms of noise. Optically, 
it's quite dim.


The clear winner here is the LT3042. Now if they made it in an 
acceptable package!
I mounted the MSOP-10 dead bug style on unetched FR4, soldered a thick 
1mm Cu wire across
the exposed pad and put the rest of the circuit on raster board. That 
was no fun, even under the

BTW the extra quiet reference of the LT3042 is a current source, so 
there is no
real justification for the repeated claims here that ECL must be noisy 
because of
its integrated current source.


I have done the writeup already:

and since we are at it:  Lab supplies

(still incomplete, but no longer high priority for me)

regards, Gerhard

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