[time-nuts] Generating a solid PPS from 10Mhz source

Attila Kinali attila at kinali.ch
Fri Jan 15 11:13:47 UTC 2016

On Thu, 14 Jan 2016 09:50:15 -0500
Vlad <time at patoka.org> wrote:

> I was thinking to make a frequency divider by using FPGA. Here is my 
> attempt to implement it using VHDL.
> This is frequency divder plus D flip-flop which I was planed to use as 
> source of 60Hz for my Telechron clock.
> However I never implement it in HW. Instead I was using STM32F4 with its 
> timers.
> The purpose was to divide 9.8304 Mhz OCXO output by 81920 to get 60Hz 
> and use the D flip-flop to keep output in sync.
> Some day I'll return to this with my soldering iron in hands. ;-)


As side note: when using an FPGA anyways, it might be good to use
something like a lambda divider [1,2].

I'm not so sure whether their explanation why this improves the noise
floor is the right one, but it definitly helps and is quite easy to

			Attila Kinali

[1] " The sampling theorem in Pi and Lambda dividers", by Calosso, Rubiola, 2013

[2] Slides to the above

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