[time-nuts] low noise multiplication to 100 MHz
Paul.Reeves at uk.thalesgroup.com
Fri Jan 22 10:15:11 UTC 2016
Why not use something like an HP5254B/C ? They give out 50MHz harmonics up to the low Ghz region, all filtered by a nice high-Q tuneable cavity. All to typical HP build quality.
Of course, they have an amount of 'not needed' circuitry and are just a bit ..... , well, bulky. Good clean output from 10MHz in though.
From: time-nuts [mailto:time-nuts-bounces at febo.com] On Behalf Of Peter Reilley
Sent: 21 January 2016 15:17
To: time-nuts at febo.com
Subject: Re: [time-nuts] low noise multiplication to 100 MHz
Have you considered synthesizers? I am using an Analog Devices AD9517
to drive a A/D
converter at 250 MHz. It has many clock outputs that are independently
It is intended for low jitter applications.
On 1/21/2016 9:43 AM, jimlux wrote:
> My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr,
> and I'm looking at alternative schemes.
> One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply
> them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and
> I've used the packaged Wenzel multipliers), and I think I have some
> spare board real estate on another board.
> The 2diode multiplier describes using 1n5711 or 1n914, but I was
> wondering if anyone has run this sort of multiplier up to 100 MHz?
> What sort of symmetry does the resulting waveform have (yeah, it's
> basically a filtered sinewave, because you're picking a harmonic, but
> I've been surprised before)?
> I'm driving an FPGA and a couple of ADCs. The ADCs have differential
> input that is 10kohms with 9pF in parallel offset from ground in the
> usual way (we're using a transformer and appropriate bias resistors).
> Not a 50 ohm load, in any case. And it wants a clock that is high for
> about 47.5% to 52.5% in one mode and much wider (30%-70% in another)..
> I need to check.
> The FPGA is less critical noise-wise, and has a AD8138 buffer in any
> case, which can fix a variety of evils.
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