[time-nuts] Re: Vernier interpolation

[Magnus Danielson]

Hi,

On 2025-07-14 20:23, Tom Verbeure via time-nuts wrote:

> I bought myself an HP 5370A yesterday at the electronics flea market. Smoke
> came out of it after plugging it in (which means I bought myself a good
> amount of entertainment for just $40), but it made me study the dual
> Vernier method of interpolation.

Service powersupply. Should be relatively trivial.

I developed a mod to reduce the noise on the reference 10 MHz, as the 
signal detect circuit generates a spurious 5 MHz. It's in the archives, 
but I just grounded a base on the diff-pair for the cursuit with a 
simple solder joint.

> I understand how it works, but I've been wondering if this is a technique
> that continues to be used or has the availability of fast and
> high-precision ADCs resulted in it being replaced by the voltage slope
> interpolation method that's used by the SR620?

I would say that the particular vernier method of the 5370 is not widely 
used. Pulse-widening has been used in some other counters, but not to 
the same resolution. The 5371, 5372 and 5373 uses a variant of the 
technique where the difference of delay of clock and trigger feeds a 
bunch of D-flip-flops (DFF). This technique was there used to achieve 
200 ps resolution or a 10 fold increate of resolution from the coarse 
clock of 500 MHz / 2 ns. This delay-difference technique have since been 
further developed in the FPGA and ASIC field, and is similar to the 
Vernier approach used for interpolation in the 5370, but you do not need 
to wait for 256 cycles and the single detection, instead this is done in 
parallel with a lot of DFFs which also have the benefit of significantly 
higher timestamping rates. In the case of 5371/5372 you can operate at 
13.33 MHz rate (75 ns).

The ADC technique took over, offering higher resolution and improved 
linearity. SR620, CNT80/81 and CNT90/91 are example of these, but the 
Wavecrest DTS 2070C/2079 brings it further. Wavecrest pushed it to 200 
fs resolution, even if trigger jitter is worse.

Further down the line, the oversampling ADC technique of Sam Stein that 
is the Symmetricom line of measurement instruments, later the TimePod 
and PhaseStation pushes this even further, avoiding aliasing problems 
and immense noise removal. These may not have the classical TIC feel, 
but we get that type of data out of it for ADEV and friends processing 
and the noise floor is way down.

> According to the August 1978 edition of HP Journal, the 5370A is using a
> custom hybrid with 5GHz transistors. I'm wondering if anyone has ever tried
> making their own TI counter using the Vernier method? (TBH, I don't think
> I've ever seen anyone build their own TI counter using slope interpolation,
> but at least high precision ADCs are available on Digikey...)

You should consider that to push performance with the technology at hand 
then, custom hybrids was the way to go. Not the same need later, and we 
even have different approaches.

The Vernier approach used is very smart for the technology at hand, but 
it has been outperformed by other technologies. Then again, it would be 
fun to experiment with tuneable delay and see what can be done. :)

Cheers,
Magnus