[time-nuts] Re: Vernier interpolation

[Tom Verbeure]

On Tue, Jul 15, 2025 at 5:00 PM Magnus Danielson via time-nuts <
time-nuts at lists.febo.com> wrote:

I developed a mod to reduce the noise on the reference 10 MHz, as the
> signal detect circuit generates a spurious 5 MHz. It's in the archives,
> but I just grounded a base on the diff-pair for the cursuit with a
> simple solder joint.
>

Do you happen to remember which thread that was? The closests post I could
find was this one:
https://www.febo.com/pipermail/time-nuts/2015-May/091973.html.


> I would say that the particular vernier method of the 5370 is not widely
> used. Pulse-widening has been used in some other counters, but not to
> the same resolution. The 5371, 5372 and 5373 uses a variant of the
> technique where the difference of delay of clock and trigger feeds a
> bunch of D-flip-flops (DFF). This technique was there used to achieve
> 200 ps resolution or a 10 fold increate of resolution from the coarse
> clock of 500 MHz / 2 ns. This delay-difference technique have since been
> further developed in the FPGA and ASIC field, and is similar to the
> Vernier approach used for interpolation in the 5370, but you do not need
> to wait for 256 cycles and the single detection, instead this is done in
> parallel with a lot of DFFs which also have the benefit of significantly
> higher timestamping rates. In the case of 5371/5372 you can operate at
> 13.33 MHz rate (75 ns).
>

I'll put that method on the list of things to study. :-)


> The Vernier approach used is very smart for the technology at hand, but
> it has been outperformed by other technologies. Then again, it would be
> fun to experiment with tuneable delay and see what can be done. :)
>

The special PLL is the real interesting part IMO.

Thanks!
Tom